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- 1 - K521F12ACD-B060 rev. 0.0, nov. 2009 samsung electronics reserves the right to change products, information and specifications without notice. products and specifications discussed herein are for reference pur poses only. all info rmation discussed herein is provided on an "as is" bas is, without warranties of any kind. this document and all information discussed herein re main the sole and exclusive property of samsung electronics. no license of any patent, copyright, mask work, tradem ark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. samsung products are not intended for use in life sup port, critical care, medical, safety equipment, or similar applications where pr oduct failure could result in loss of li fe or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. for updates or additional information about samsung products, contact your nearest samsung office. all brand names, trademarks and registered tradem arks belong to their respective owners. ? 2009 samsung electronics co., ltd. all rights reserved. preliminary mcp specification 1gb (128m x8) nand flash + 512mb (32m x16) mobile ddr sdram datasheet www.datasheet.co.kr datasheet pdf - http://www..net/
- 2 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary revision history revision no. history draft date remark editor 0.0 initial issue. - 1gb nand flash w-die_ ver 0.0 - 512mb mobile ddr sdram i-die_ver 0.1 nov. 10, 2009 preliminary h.y.min www.datasheet.co.kr datasheet pdf - http://www..net/
- 3 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 1. features ? operating temperature : -25 c ~ 85 c ? package : 107ball fbga type - 10.5x13x1.2mmt, 0.8mm pitch ? voltage supply : 1.7v ~ 1.95v ? organization - memory cell array : (128m + 4m) x 8bit for 1gb - data register : (2k + 64) x 8bit ? automatic program and erase - page program : (2k + 64)byte - block erase : (128k + 4k)byte ? page read operation - page size : (2k + 64)byte - random read : 40 s(max. tbd) - serial access : 42ns(min. tbd) ? fast write cycle time - page program time : 250 s(typ. tbd) - block erase time : 2ms(typ. tbd) ? command/address/data multiplexed i/o port ? hardware data - program/erase lockout during power transitions ? reliable cmos floating-gate technology -endurance : 100k program/erase cycles with 1bit/512byte ecc for x8, ? command driven operation unique id for copyright protection ? vdd/vddq = 1.8v/1.8v ? double-data-rate architecture; tw o data transfers per clock cycle ? bidirectional data strobe(dqs) ? four banks operation ? differential clock inputs(ck and ck ) ? mrs cycle with address key programs - cas latency ( 3 ) - burst length ( 2, 4, 8, 16 ) - burst type (sequential & interleave) ? emrs cycle with address key programs - partial array self refresh ( full, 1/2, 1/4 array ) - output driver strength control ( full, 1/2, 1/4, 1/8, 3/4, 3/8, 5/8, 7/8 ) ? internal temperature compensated self refresh ? all inputs except data & dm are sampled at the positive going edge of the system clock(ck). ? data i/o transactions on both edges of data strobe, dm for masking. ? edge aligned data output, center aligned data input. ? no dll; ck to dqs is not synchronized. ? ldm - udm for write masking only. ? clock stop capability. ? auto refresh duty cycle - 7.8us note : 1) cas latency - dm is internally loaded to match dq and dqs identically. operating frequency ddr333 speed @cl3 1) 166mhz address configuration organization bank row column 32mx16 ba0,ba1 a0 - a12 a0 - a9 www.datasheet.co.kr datasheet pdf - http://www..net/
- 4 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 2. general description the k521f12acd is a multi chip package memory which combines 1gbit nand flash memory and 512mbi t ddr synchronous high data rate dynamic ram. nand cell provides the most cost-effective solution for the solid state application market. a program operation can be performe d in typical 250 s(tbd) on the (2k+64)byte page and an erase operation can be performed in ty pical 2ms on a (128k+4k)byte block. data in the data register can be read out at 42ns cycle time per byte. the i/o pins se rve as the ports for address and data input/ output as well as command input. the on-ch ip write controller auto- mates all program and erase functions including pulse repetition, where required, and internal verification and margining of da ta. even the write-intensive systems can take advantage of the device s extended reliability of 100k program/erase cycles by providing ecc(error correcting code) with real time mapping-out algorithm. the device is an optimum solution for large nonvolatile storage applications such as solid state file st orage and other portable applications requiri ng non-volatility. in 512mb mobile ddr, synchronous design make a device controlled precisely with the us e of system clock. range of operating fre quencies, program- mable burst length and programmable latencies allow the same dev ice to be useful for a variety of high bandwidth, high performa nce memory system applications. the k521f12acd is suitable for use in data me mory of mobile communication system to reduce not only mount area but also power c onsumption. this device is available in 107-ball fbga type. www.datasheet.co.kr datasheet pdf - http://www..net/
- 5 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 3. pin configuration 107 fbga: top view (ball down) - 12345678910 a - dnu ------ dnu dnu bdnu nc dq0d vddd vssn vccn nc a3d nc dnu c - vssd dq2d dq1d clen /cen a0d a1d a2d - d - vddqd dq4d dq3d alen /wen ba0d ba1d a10d - e - vssqd dq6d dq5d /ren r/b n /rasd nc /csd - f - vddqd ldqsd dq7d /wpn nc /casd /wed vssd - g - vssd ldmd /ckd nc nc a12d cked vddd - h - vddd udmd ckd nc nc a8d a9d a11d - j - vssqd udqsd dq8d io0n io2n io4n io6n a7d - k - vddqd dq9d dq10d nc nc nc nc a6d - l - vssqd dq11d dq12d io1n io3n io5n io7n a5d - m - vddd dq13d dq14d nc nc nc nc a4d - ndnu nc dq15d vssd vssn vccqn vccn vssn nc dnu p dnu dnu ------ dnu dnu nand flash mobile dram power ground nc/dnu www.datasheet.co.kr datasheet pdf - http://www..net/
- 6 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 4. pin description pin name pin function(mobile dram) pin name pin function(nand flash) ckd, /ckd differential system clock /cen chip enable cked clock enable /ren read enable /csd chip select /wpn write protection /rasd row address strobe /wen write enable /casd column address strobe alen address latch enable /wed write enable clen command latch enable a0d ~ a12d address input r/b n ready/busy output ba0d ~ ba1d bank address input io0n ~ io7n data input/output ldmd,udmd lower / upper input data mask vccn power supply ldqsd , udqsd lower / upper data strobe vccqn data out power dq0d ~ dq15d data input/output vssn ground vddd power supply vddqd data out power pin name pin function vssd ground dnu do not use vssqd dq ground nc no connection www.datasheet.co.kr datasheet pdf - http://www..net/
- 7 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 5. ordering information k5 2 1f 12 a c d - b 0 60 samsung mcp memory(2chips) device type nand flash + mobile ddr nand flash density, organization 1f : 1gbit, x8 flash block architecture c : uniform block version d : 5th generation m-ddr speed 60 : 6.0ns (333mbps@cl3) operating voltage a: 1.8v / 1.8v package b : fbga(hf, osp lf) mobile ddr density, organization 12 : 512mbit, x16 nand flash speed 0 : none www.datasheet.co.kr datasheet pdf - http://www..net/
- 8 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 6. functional block diagram /wpn clen /wen /ren r/b n /cen io0n to io7n /csd /casd /rasd cked /wed ckd, /ckd a0d ~ a12d ldmd, udmd ba0d ~ ba1d ldqsd, udqsd alen 1gb nand flash memory dq0d to dq15d 512mb mobile ddr sdram vddd vddqd vccn vccqn vssn vssd vssqd www.datasheet.co.kr datasheet pdf - http://www..net/
- 9 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 7. package dimension 107-ball fine pitch ball grid array package (measured in millimeters) units:millimeters 0.10 max 0.45 0.05 0.32 0.05 1.10 0.10 top view 10.50 0.10 13.00 0.10 #a1 107- ? 0.45 0.05 0 . 8 0 0.20 m a b ? (datum a) 1 42 765 3 8 #a1 index mark 10.50 0.10 13.00 0.10 0 . 8 0 9 10 0.80 x 9 = 7.20 0.80 x 13 = 10.40 a b c e g d f h j l k m n p (datum b) 5.20 3.60 bottom view a b www.datasheet.co.kr datasheet pdf - http://www..net/
- 10 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 1gb (128m x8) nand flash w-die www.datasheet.co.kr datasheet pdf - http://www..net/
- 11 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary figure 1. functional block diagram v cc x-buffers command i/o buffers & latches latches & decoders y-buffers latches & decoders register control logic & high voltage generator global buffers output driver v ss a 12 - a 27 a 0 - a 11 command ce re we cle wp i/0 0 i/0 7 v cc v ss ale 1,024m + 32m bit for 1gb nand flash array y-gating data register & s/a (x8) figure 2. array organization 2k bytes 64 bytes 2k bytes 8 bit 64 bytes 1 block = 64 pages (128k + 4k) byte i/o 0 ~ i/o 7 1 page = (2k + 64)bytes 1 block = (2k + 64)byte x 64 pages = (128k + 4k) bytes 1 device = (2k+64)b x 64pages x 1,024 blocks = 1,056 mbits for 1gb page register 1,024 blocks for 1gb (x8) table 1. array address : (x8) note : column address : starting address of the register. * l must be set to "low". * the device ignores any additional input of address cycles than required. i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 address 1st cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 column address 2nd cycle a 8 a 9 a 10 a 11 *l *l *l *l column address 3rd cycle a 12 a 13 a 14 a 15 a 16 a 17 a 18 a 19 row address 4th cycle a 20 a 21 a 22 a 23 a 24 a 25 a 26 a 27 row address www.datasheet.co.kr datasheet pdf - http://www..net/
- 12 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary figure 3. functional block diagram v cc x-buffers command i/o buffers & latches latches & decoders y-buffers latches & decoders register control logic & high voltage generator global buffers output driver v ss a 11 - a 26 a 0 - a 10 command ce re we cle wp i/0 0 i/0 15 v cc v ss ale 1,024m + 32m bit for 1gb nand flash array y-gating data register & s/a (x16) figure 4. figure 2-2. array organization 1k words 32 words 1k words 16 bit 32 words 1 block = 64 pages (64k + 2k)word i/o 0 ~ i/o 15 1 page = (1k + 32)word 1 block = (1k + 32)word x 64 pages = (64k + 2k)words 1 device = (1k + 32)word x 64pages x 1,024 blocks = 1,056 mbits for 1gb page register 1,024 blocks for 1gb (x16) table 2. array address : (x16) note : column address : starting address of the register. * l must be set to "low". * the device ignores any additional input of address cycles than required. i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8~i/o 15 address 1st cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 *l column address 2nd cycle a 8 a 9 a 10 *l *l *l *l *l *l column address 3rd cycle a 11 a 12 a 13 a 14 a 15 a 16 a 17 a 18 *l row address 4th cycle a 19 a 20 a 21 a 22 a 23 a 24 a 25 a 26 *l row address www.datasheet.co.kr datasheet pdf - http://www..net/
- 13 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 1. product introduction nand flash memory has addresses multiplexed into 8 i/os(x16 device case : lower 8 i/os). this scheme dram atically reduces pin c ounts and allows sys- tem upgrades to future densities by maintaining consistency in system board design. command, address and data are all written t hrough i/o's by bringing we to low while ce is low. those are latched on the rising edge of we . command latch enable(cle) and address latch enable(ale) are used to mul- tiplex command and address respectively, via t he i/o pins. some commands require one bus cycle. for example, reset command, sta tus read com- mand, etc require just one cycle bus. some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution. page read and page program need the same four address cycles following the required command input. in block erase operation, however, only the two row address cycles are used. device operations are selected by writing specific commands into the command register. table 3 defines the specific commands of the device. in addition to the enhanced architecture and interface, the devic e incorporates copy-back program feature from one page to anot her page without need for transporting the data to and from the external buffer memory. since the time-consuming serial access and data-input cycles are removed, system per- formance for solid-state disk appl ication is signifi cantly increased. table 3. command sets note : 1) random data input/output can be executed in a page. caution : any undefined command inputs are prohibited ex cept for above command set of table 3. function 1st cycle 2nd cycle acceptable command during busy read 00h 30h read id 90h - read for copy back 00h 35h reset ffh - o page program 80h 10h copy-back program 85h 10h block erase 60h d0h random data input 1) 85h - random data output 1) 05h e0h read status 70h - o www.datasheet.co.kr datasheet pdf - http://www..net/
- 14 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 1.1 absolute maximum ratings note : 1) minimum dc voltage is -0.6v on input/output pins. during tran sitions, this level may undershoo t to -2.0v for periods <30ns. maximum dc voltage on input/output pins is vcc+0.3v which, during transitions, may overshoot to vcc+2.0v for periods <20ns. 2) permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data shee t. exposure to absolute maximum ra ting conditions for extended per iods may affect reliability. 1.2 recommended operating conditions (voltage reference to gnd, t a =-25 to 85 c) 1.3 dc and operating characteristics (recommended operating conditions otherwise noted.) note : 1) v il can undershoot to -0.4v and v ih can overshoot to v cc +0.4v for durations of 20 ns or less. 2) typical value is measured at vcc=1.8v, t a =25 c. not 100% tested. parameter symbol rating unit voltage on any pin relative to vss vcc -0.6 to + 2.45 v vin -0.6 to + 2.45 vi/o -0.6 to vcc + 0.3 (< 2.45v) temperature under bias tbias -30 to +125 c storage temperature tstg -65 to +150 c short circuit current ios 5 ma parameter symbol min typ. max unit supply voltage v cc 1.7 1.8 1.95 v supply voltage v ss 000v parameter symbol test conditions min typ max unit operating current page read with serial access i cc 1 t rc =42ns ce =v il , i out =0ma - 15 25 ma program i cc 2 -- erase i cc 3 -- stand-by current(ttl) i sb 1ce =v ih , wp =0v/v cc --1 stand-by current(cmos) i sb 2ce =v cc -0.2, wp =0v/v cc -1050 a input leakage current i li v in =0 to v cc (max) - - 10 output leakage current i lo v out =0 to v cc (max) - - 10 input high voltage v ih 1) - 0.8xv cc - v cc +0.3 v input low voltage, all inputs v il 1) --0.3- 0.2xv cc output high voltage level v oh i oh =-100 a vcc-0.1 - - output low voltage level v ol i ol =100ua --0.1 output low current(r/b ) i ol (r/b )v ol =0.1v 34-ma www.datasheet.co.kr datasheet pdf - http://www..net/
- 15 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 1.4 valid block note : 1) the device may include initial invalid blocks when first ship ped. additional invalid blocks may develop while being used. th e number of valid blocks is presented with both cases of invalid blocks considered . invalid blocks are defined as bl ocks that contain one or more bad bits. do not erase or pro gram factory-marked b ad blocks. refer to the attached technical notes for appropriate management of invalid blocks. 2) the 1st block, which is placed on 00h block address, is guar anteed to be a valid block up to 1k program/erase cycles with x 8 : 1bit/ 512byte, x16 : 1bit/256word ecc. 1.5 ac test condition (ta=-25 to 85 c, vcc=1.7v~1.95v unless otherwise noted) 1.6 capacitance (ta=25 c, vcc=1.8v, f=1.0mhz) note : capacitance is periodically sampled and not 100% tested. 1.7 mode selection note : 1) x can be v il or v ih . 2) wp should be biased to cmos high or cmos low for standby. parameter symbol min typ. max unit 1gb n vb 1,004 - 1,024 blocks parameter value input pulse levels 0v to vcc input rise and fall times 5ns input and output timing levels vcc/2 output load 1 ttl gate and cl=30pf item symbol test condition min max unit input/output capacitance (mono) c i/o v il =0v -10pf input capacitance (mono) c in v in =0v -10pf input/output capacitance (ddp) c i/o v il =0v -20pf input capacitance (ddp) c in v in =0v -20pf cle ale ce we re wp mode hll hx read mode command input l h l h x address input(5clock) hll hh write mode command input l h l h h address input(5clock) l l l h h data input l l l h x data output x x x x h x during read(busy) x x x x x h during program(busy) x x x x x h during erase(busy) x x 1) x x x l write protect xxhxx 0v/vcc 2) stand-by www.datasheet.co.kr datasheet pdf - http://www..net/
- 16 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 1.8 read / program / erase characteristics note : 1) typical program time is defined as the time within which mo re than 50% of the whole pages are programmed at 1.8v vcc and 25 c temperature. 1.9 ac timing characteristics for command / address / data input note : 1) the transition of the corresponding c ontrol pins must occur only once while we is held low 2) t adl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle parameter symbol min typ max unit program time t prog - 250(tbd) 750(tbd) s number of partial program cycles in the same page n op - - 4 cycles block erase time t bers -2(tbd)10(tbd)ms parameter symbol min max unit cle setup time t cls 1) 21 - ns cle hold time t clh 5-ns ce setup time t cs 1) 21 - ns ce hold time t ch 5-ns we pulse width t wp 21 - ns ale setup time t als 1) 21 - ns ale hold time t alh 5-ns data setup time t ds 1) 20 - ns data hold time t dh 5-ns write cycle time t wc 40 - ns we high hold time t wh 10 - ns address to data loading time t adl 2) 100 - ns www.datasheet.co.kr datasheet pdf - http://www..net/
- 17 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 1.10 ac characteristics for operation note : 1) if reset command(ffh) is written at ready state, the device goes into busy for maximum 5 s. parameter symbol min max unit data transfer from cell to register t r -40 s ale to re delay t ar 10 - ns cle to re delay t clr 10 - ns ready to re low t rr 20 - ns re pulse width t rp 21 - ns we high to busy t wb - 100 ns wp low to we low (disable mode) t ww 100 - ns wp high to we low (enable mode) read cycle time t rc 42 - ns re access time t rea -30ns ce access time t cea -35ns re high to output hi-z t rhz - 100 ns ce high to output hi-z t chz -30ns ce high to ale or cle don?t care t csd 0-ns re high to output hold t roh 15 - ns ce high to output hold t coh 15 - ns re high hold time t reh 10 - ns output hi-z to re low t ir 0-ns re high to we low t rhw 100 - ns we high to re low t whr 60 - ns device resetting time(read/program/erase) t rst - 5/10/500 1) s www.datasheet.co.kr datasheet pdf - http://www..net/
- 18 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 2. nand flash technical notes 2.1 initial invalid block(s) initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by samsung. the information regarding the initial invalid block(s) is called the initial inva lid block information. devices with initial invalid block(s) h ave the same quality level as devices with all valid blocks and have the same ac and dc characteristics. an initial invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a sele ct transistor. the system design must be able to mask out the initial invalid block(s) via address mapping. the 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1k program/erase cycles with x8:1bit/ 512byte, x16:1bit/256word ecc. 2.2 identifying initial invalid block(s) all device locations are erased(ffh) except locations where the in itial invalid block(s) informat ion is written prior to shippi ng. the initial invalid block(s) status is defined by the 1st byte(1st word) in the spare area. samsung makes sure that either the 1st or 2nd page of every init ial invalid block has non-ffh data at the column address of 2048(x16:1024). since the initial inva lid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. therefore, the system must be able to recognize the initial invalid block(s) based on the original initial invalid block information and create the initial invalid block table via the fo llowing suggested flow chart(fi gure 5). any intentional erasur e of the original initial invalid block information is prohibited. figure 5. flow chart to create initial invalid block table * check "ffh(x16:ffffh)" at the start set block address = 0 check increment block address last block ? end no yes yes create (or update) no initial of the 1st and 2nd page in the block invalid block(s) table "ffh(x16:ffffh)" column address 2048(x16:1024) www.datasheet.co.kr datasheet pdf - http://www..net/
- 19 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary nand flash technical notes (continued) 2.3 error in write or read operation within its life time, additional invalid bl ocks may develop with nand flash memory. refer to the qualification report for the a ctual data. block replacement should be done upon erase or program error. ecc : error correcting code --> hamming code example) 1bit correction & 512-byte note : a repetitive page read operation on the same block without erase may cause bit errors, which could be accumulated over time an d exceed the coverage of ecc. software scheme such as caching into ram is recommended. program flow chart failure mode detection and countermeasure sequence write erase failure status read after erase --> block replacement program failure status read after program --> block replacement read up to 1 bit-failure verity ecc -> ecc correction start i/o 6 = 1 ? i/o 0 = 0 ? no * write 80h write address write data write 10h read status register program completed or r/b = 1 ? program error yes no yes : if program operation results in an error, map out the block including the page in error and copy the target data to another block. * www.datasheet.co.kr datasheet pdf - http://www..net/
- 20 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary nand flash technical notes (continued) block replacement * step1 when an error happens in the nth page of the bloc k ?a? during erase or program operation. * step2 copy the data in the 1st ~ (n-1)th page to the same location of another free block. (block ?b?) * step3 then, copy the nth page data of the block ?a? in the buffer memory to the nth page of the block ?b?. * step4 do not erase or program to block ?a? by creating an ?invalid block? table or other appropriate scheme. erase flow chart read flow chart start i/o 6 = 1 ? i/o 0 = 0 ? no * write 60h write block address write d0h read status register or r/b = 1 ? erase error yes no : if erase operation results in an error, map out the failing block and replace it with another block. * erase completed yes start verify ecc no write 00h write address read data ecc generation reclaim the error page read completed yes write 30h buffer memory of the controller. 1st block a block b (n-1)th nth (page) { 1st (n-1)th nth (page) { an error occurs. 1 2 www.datasheet.co.kr datasheet pdf - http://www..net/
- 21 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary nand flash technical notes (continued) 2.4 addressing for program operation within a block, the pages must be programmed consecutively from the lsb(l east significant bit) page of the block to the msb(mos t significant bit) pages of the block. random page address programming is prohibited. in th is case, the definition of lsb page is the lsb among the page s to be programmed. therefore, lsb doesn't need to be page 0. from the lsb page to msb page data in: data (1) data (64) (1) (2) (3) (32) (64) data register page 0 page 1 page 2 page 31 page 63 ex.) random page program (prohibition) data in: data (1) data (64) (2) (32) (3) (1) (64) data register page 0 page 1 page 2 page 31 page 63 : : : : www.datasheet.co.kr datasheet pdf - http://www..net/
- 22 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 2.5 system interface using ce don?t-care. for an easier system interface, ce may be inactive during the data-loading or serial access as shown below. the internal 2,112byte(1,056word) data reg- isters are utilized as separate buffers for this operation and t he system design gets more flexible. in addition, for voice or audio applications which use slow cycle time on the order of p -seconds, de-activating ce during the data-loading and serial access woul d provide significant savings in power con- sumption. figure 6. program operation with ce don?t-care. ce we t wp t ch t cs address(4cycles) 80h data input ce cle ale we data input ce don?t-care 10h t cea out t rea ce re i/o x i/ox | | | | | | | | | | | | figure 7. read operation with ce don?t-care. address(4cycle) 00h ce cle ale we data output(serial access) ce don?t-care r/b t r re 30h i/ox | | | | | | | | | | | | note : device i/o data address i/ox data in/out col. add1 col. add2 row add1 row add2 1gb(x8) i/o 0 ~ i/o 7 ~2,112byte a0~a7 a8~a11 a12~a19 a20~a27 1gb(x16) i/o 0 ~ i/o 15 ~1,056word a0~a7 a8~a10 a11~a18 a19~a26 www.datasheet.co.kr datasheet pdf - http://www..net/
- 23 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 3. timing diagrams 3.1 command latch cycle ce we cle ale command t cls t cs t clh t ch t wp t als t alh t ds t dh i/ox www.datasheet.co.kr datasheet pdf - http://www..net/
- 24 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 3.2 address latch cycle ce we cle ale col. add1 t cs t wc t wp t als t ds t dh t alh t als t wh t wc t wp t ds t dh t alh t als t wh t wc t wp t ds t dh t alh t als t wh t ds t dh t wp i/ox col. add2 row add1 row add2 t alh t cls 3.3 input data latch cycle ce cle we din 0 din 1 din final ale t als t clh t wc t ch t ds t dh t ds t dh t ds t dh t wp t wh t wp t wp | | | i/ox | | | www.datasheet.co.kr datasheet pdf - http://www..net/
- 25 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 3.4 * serial access cycle after read (cle=l, we =h, ale=l) re ce r/b dout dout dout t rc t rea t rr t roh t rea t reh t rea t coh t rhz | | | | i/ox t chz t rhz t rp note : transition is measured at r 200mv from steady state voltage with load. this parameter is sampled and not 100% tested. 3.5 ce we cle re 70h status output t clr t clh t wp t ch t ds t dh t rea t ir t rhoh t coh t whr t cea t cls i/ox t chz t rhz t cs status read cycle www.datasheet.co.kr datasheet pdf - http://www..net/
- 26 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 3.6 read operation ce cle r/b we ale re busy 00h col. add1 col. add2 row add1 dout n dout n+1 column address row address t wb t ar t r t rc t rhz t rr dout m t wc | | | row add2 30h t clr i/ox 3.7 read operation (intercepted by ce ) ce cle r/b we ale re busy 00h dout n dout n+1 dout n+2 row address column address t wb t ar t chz t r t rr t rc 30h i/ox col. add1 col. add2 row add1 row add2 t coh t clr t csd www.datasheet.co.kr datasheet pdf - http://www..net/
- 27 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 3.8 random data output in a page ce cle r/b we ale re busy 00h dout n dout n+1 row address column address t w b t ar t r t rr 30h 05h column address dout m dout m+1 i/ox col. add1 col. add2 row add1 row add2 col add1 col add2 t clr e0h t whr t rea t rc t rhw www.datasheet.co.kr datasheet pdf - http://www..net/
- 28 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 3.9 page program operation note : t adl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. ce cle r/b we ale re 80h 70h i/o 0 din n din 10h m serialdata input command column address row address 1 up to m word serial input program command read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc t wc t wc i/ox co.l add1 col. add2 row add1 row add2 t adl t whr www.datasheet.co.kr datasheet pdf - http://www..net/
- 29 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 3.10 page program operati on with random data input ce cle r/b we ale re 80h 70h i/o 0 din n din 10h m serial data input command column address row address serial input program command read status command t prog t wb t wc t wc 85h random data input command column address t wc din j din k serial input i/ox col. add1 col. add2 row add1 row add2 col. add1 col. add2 t adl t adl t whr note : 1) tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. 2) after serial input of data for random data input, status read(70h) command can be issued for reading status, and only status bit(i/o 6) is valid. www.datasheet.co.kr datasheet pdf - http://www..net/
- 30 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 3.11 copy-back program operation with random data input 00h i/o x 85h column address row address read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc | busy t wb t r busy | 10h copy-back data input command 35h column address row address data 1 data n | | col add1 col add2 row add1 row add2 col add1 col add2 row add1 row add2 70h t adl t whr data 1 data n | | t rc ce cle r/b we ale re i/ox note : 1) tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. note : 1) tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. www.datasheet.co.kr datasheet pdf - http://www..net/
- 31 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 3.12 block erase operation ce cle r/b we ale re 60h erase command read status command i/o 0 =1 error in erase d0h 70h i/o 0 busy t wb t bers i/o 0 =0 successful erase row address t wc | auto block erase setup command i/ox row add1 row add2 t whr www.datasheet.co.kr datasheet pdf - http://www..net/
- 32 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 3.13 read id operation ce cle we ale re 90h read id command maker code device code 00h ech t rea address 1cycle i/ox t ar device 4th cyc. code 3rd cyc. 5th cyc. 3.13.1. id definition table 90 id : access command = 90h device device code (2nd cycle) 3rd cycle 4th cycle 5th cycle 1gb(x8) a1h 00h 15h 40h 1gb(x16) b1h 00h 55h 40h description 1 st byte 2 nd byte 3 rd byte 4 th byte 5 th byte maker code device code internal chip number page size, block size,redundant area size, organization plane number, plane size, ecc level www.datasheet.co.kr datasheet pdf - http://www..net/
- 33 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 3rd id data 4th id data 5th id data item description i/o # 7 6 5 4 3 2 1 0 internal chip number 1 2 4 8 0 0 1 1 0 1 0 1 cell type 2 level cell 4 level cell 8 level cell 16 level cell 0 0 1 1 0 1 0 1 number of simultaneously programmed pages 1 2 4 8 0 0 1 1 0 1 0 1 interleave program between multii-chips not supported supported 0 1 cache program not supported supported 0 1 item description i/o # 7 6 5 4 3 2 1 0 page size (without redundant area) 1kb 2kb 4kb 8kb 0 0 1 1 0 1 0 1 block size (without redundant area) 64kb 128kb 256kb 512kb 0 0 1 1 0 1 0 1 redundant area size (byte/512byte) 8 16 reserved reserved 0 0 1 1 0 1 0 1 organization x8 x16 0 1 reserved 0 or 1 item description i/o # 7 6 5 4 3 2 1 0 ecc level 1bit ecc/512byte 2bit ecc/512byte 4bit ecc/512byte reserved 0 0 1 1 0 1 0 1 plane number 1 2 4 8 0 0 1 1 0 1 0 1 plane size (without redundant area) 64kb 128kb 256kb 512kb 1gb 2gb 4gb 8gb 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 reseved reserved 0 www.datasheet.co.kr datasheet pdf - http://www..net/
- 34 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 4. device operation 4.1 page read page read is initiated by writing 00h-30h to the command register along with four addr ess cycles. after initial power up, 00h c ommand is latched. there- fore only four address cycles and 30h command initiates that ope ration after initial power up. the 2,112 bytes(1,056 wrods) of data within the selected page are transferred to the data registers in 40 p s(t r ) typically. the system controller can detect the co mpletion of this data transfer(tr) by analyzing the output of r/b pin. once the data in a page is loaded into the data register s, they may be read out in 42ns cycle time by sequentially pulsin g re . the repet- itive high to low transitions of the re clock make the device output the data starting from the selected column address up to the last column address. the device may output random data in a page instead of the cons ecutive sequential data by writing random data output command. t he column address of next data, which is going to be out, may be changed to the addr ess which follows random data output command. random data out put can be operated multiple times regardless of how many times it is done in a page. figure 8. read operation address(4cycle) 00h col. add.1,2 & row add.1,2 data output(serial access) data field spare field ce cle ale r/b we re t r 30h i/ox | | | | | | www.datasheet.co.kr datasheet pdf - http://www..net/
- 35 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 4.2 page program the device is programmed basically on a page basis, but it does allow multiple partial page programming of a byte(a word) or co nsecutive byte up to 2,112 bytes(1,056 wrods), in a single page program cycle. the num ber of consecutive partial page programming operation within t he same page without an intervening erase operation must not exceed 4 times for a si ngle page. the addressing should be done in sequential order in a block. a page program cycle consists of a serial data loading period in which up to 2,112 bytes(1,056 wrods) of data may be loaded into the data regi ster, followed by a non-vol- atile programming period where the loaded data is programmed into the appropriate cell. the serial data loading period begins by inputting the serial da ta input command(80h), followed by the four cycle address input s and then serial data loading. the bytes(words) other than those to be programmed do not need to be loaded. the device supports random data input in a page. the column address for the next data, which will be entered, may be changed to the address which follows random data input command(85h). r andom data input may be operated multiple times regardless of how many times it is done in a page. the page program confirm command(10h) initiates the programming pr ocess. writing 10h alone without previously entering the seri al data will not initiate the programming process. the internal write state controller aut omatically executes the algorit hms and timings necessary for pr ogram and verify, thereby freeing the system controller for other tasks. once the program process starts, the read status register command may be entered to read the status reg- ister. the system controller can detect the comp letion of a program cycle by monitoring the r/b output, or the status bit(i/o 6) of the status register. only the read status command and reset command are valid while programmi ng is in progress. when the page program is complete, the wr ite status bit(i/ o 0) may be checked(figure 9). the internal write verify detects only errors for "1"s that are not successfully programmed to " 0"s. the command register remains in read status command mode until another valid command is written to the command register. figure 9. program & read status operation 80h r/b address & data input i/o0 pass data 10h 70h fail t prog i/ox col. add.1,2 & row add.1,2 "0" "1" figure 10. random data input in a page 80h r/b address & data input i/o0 pass 10h 70h fail t prog 85h address & data input i/ox col. add.1,2 & row add1,2 col. add.1,2 data data "0" "1" www.datasheet.co.kr datasheet pdf - http://www..net/
- 36 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 4.3 copy-back program copy-back program with read for copy-back is configured to quick ly and efficiently rewrite data stored in one page without data re-loading when the bit error is not in data stored. since the ti me-consuming re-loading cycles are removed, the system performance is improved. the be nefit is es pecially obvi- ous when a portion of a block is updated and the rest of the bloc k also needs to be copied to the newly assigned free block. co py-back operation is a sequential execution of read for copy-back and of copy-back program with the destination page address. a read operation with "3 5h" command and the address of the source page moves the whole 2,112 bytes(1,056 wrod s) data into the internal data buffer. a bit error is checked by sequential reading the data output. in the case where there is no bit error, the data do not need to be reloaded. therefore copy-back program operatio n is initiated by issuing page-copy data-input command (85h) with destination page address. actual programming operation begins after program confirm com mand (10h) is issued. once the program process starts, the read status register command (70h) may be entered to read the status register. the system controller can detect the completion of a program cycle by monitoring the r/b output, or the status bit(i/o 6) of the stat us register. when the copy-back program is complete, the write status bit(i/o 0) may be checked(figure 11 & figure 12). the command register remains in read status comma nd mode until another valid command is written to the command register. during copy-back program, data modificati on is possible using random data input command (85h) as shown in figure 12. figure 11. page copy-back program operation note : 1) copy-back program operation is allowed only within the same memory plane. figure 12. page copy-back program operation with random data input 4.4 block erase the erase operation is done on a block basis. block address loading is accomplished in tw o cycles initiated by an erase setup c ommand(60h). only block address is valid while page address is ignored. the eras e confirm command(d0h) followi ng the block address loading initia tes the internal erasing process. this two-step sequence of setup followed by executi on command ensures that memory contents are not accidentally erased due to external noise conditions. at the rising edge of we after the erase confirm command input, the internal write cont roller handles erase and erase- verify. when the erase operation is completed, the write status bit(i/o 0) ma y be checked. figure 13 details the sequence. figure 13. block erase operation 60h row add 1,2 r/b address input(2cycle) i/o0 pass d0h 70h fail t bers i/ox "0" "1" "0" "1" 00h r/b add.(4cycles) i/o0 pass fail t prog t r source address destination address i/ox col. add.1,2 & row add.1,2 col. add.1,2 & row add.1,2 35h data output 85h add.(4cycles) 10h 70h | | r/b source address destination address there is no limitation for the number of repetition. i/ox col. add.1,2 & row add.1,2 col. add.1,2 & row add.1,2 col. add.1,2 00h add.(4cycles) 35h t r data output 85h add.(4cycles) data | | 85h add.(2cycles) data 10h t prog 70h www.datasheet.co.kr datasheet pdf - http://www..net/
- 37 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 4.5 read status the device contains a status register whic h may be read to find out whether program or erase operation is completed, and whethe r the program or erase operation is completed successfully. after writing 70h command to the command register, a read cycle outputs the content of the status register to the i/ o pins on the falling edge of ce or re , whichever occurs last. this two line control allows the system to poll the progress of each device in multiple mem- ory connections even when r/b pins are common-wired. re or ce does not need to be toggled for updated status . refer to table 4 for specific status register definitions. the command register remains in status r ead mode until further commands are issued to it. therefore, if t he status register is read during a random read cycle, the read command(00h) should be given befor e starting read cycles. table 4. status register definition for 70h command note : 1) i/os defined ?not use? are recommended to be masked out when read st atus is being executed. i/o page program block erase read definition i/o 0 pass/fail pass/fail not use pass : "0" fail : "1" i/o 1 not use not use not use don?t -cared i/o 2 not use not use not use don?t -cared i/o 3 not use not use not use don?t -cared i/o 4 not use not use not use don?t -cared i/o 5 not use not use not use don?t -cared i/o 6 ready/busy ready/busy ready/busy busy : "0" ready : "1" i/o 7 write protect write protect write protect protected : "0" not protected : "1" www.datasheet.co.kr datasheet pdf - http://www..net/
- 38 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 4.6 read id the device contains a product identificati on mode, initiated by writing 90h to the command register, followed by an address inp ut of 00h. five read cycles sequentially output the manufacturer code(ech), and the device code and 3rd, 4th, 5th cycle id respectively. the command regis ter remains in read id mode until further commands are issued to it. figure 14 shows the operation sequence. figure 14. read id operation ce cle i/o x ale re we 90h 00h address. 1cycle maker code device code t cea t ar t rea t whr t clr device 4th cyc. code ech 3rd cyc. 5th cyc. 4.7 reset the device offers a reset feature, executed by writing ffh to the command register. when the device is in busy state during ran dom read, program or erase mode, the reset operation will abort these operations. the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. the command register is cleared to wait fo r the next command, and the status register is cleared to value c0h when wp is high. if the device is already in reset state a new reset command will be accepted by the command register. the r/b pin changes to low for trst after the reset command is written. refer to figure 15 below. figure 15. reset operation ffh i/o x r/b t rst table 5. device status device device code (2nd cycle) 3rd cycle 4th cycle 5th cycle 1gb(x8) a1h 00h 15h 40h 1gb(x16) b1h 00h 55h 40h after power-up after reset operation mode mode 00h command is latched waiting for next command www.datasheet.co.kr datasheet pdf - http://www..net/
- 39 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 4.8 ready/ busy the device has a r/b output that provides a hardware method of indicating the comp letion of a page program, erase and random read completion. the r / b pin is normally high but transit ions to low after program or erase command is written to the command register or random read i s started after address loading. it returns to high when the internal controller has finished the operation. the pin is an open-drain driver thereby al lowing two or more r/b outputs to be or-tied. because pull-up resi stor value is related to tr(r/b ) and current drain during busy(ibusy) , an appropriate value can be obtained with the fol- lowing reference chart(fig.17). its valu e can be determined by the following guidance. figure 16. rp vs tr ,tf & rp vs ibusy rp value guidance where i l is the sum of the input currents of all devices tied to the r/b pin. rp(max) is determined by maxi mum permissible limit of tr v cc r/b open drain output device gnd rp ibusy busy ready vcc voh tf tr vol 1.8v device - v ol : 0.1v, v oh : v cc -0.1v c l vcc tr,tf [s] ibusy [a] rp(ohm) ibusy tr @ vcc = 1.8v, ta = 25 c , c l = 30pf 1k 2k 3k 4k 100n 200n 2m 1m 30 tf 60 90 120 1.7 1.7 1.7 1.7 1.70 0.85 0.57 0.43 rp(min, 1.8v part) = v cc (max.) - v ol (max.) i ol + i l = 1.85v 3ma + i l www.datasheet.co.kr datasheet pdf - http://www..net/
- 40 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 5. data protection & power up sequence the device is designed to offer pr otection from any involuntary program/erase du ring power-transitions. an internal voltage det ector disables all functions whenever vcc is below about 1.1v. wp pin provides hardware protecti on and is recommended to be kept at v il during power-up and power-down. a recovery time of minimum 1ms is required before internal circuit gets ready for any command sequences as shown in figure 17. th e two step command sequence for program/erase provides additional software protection. figure 17. ac waveforms for power transition v cc wp high we ready/busy 5 ms max operation 1ms ~ 1.5v ~ 1.5v invalid don?t care don?t care www.datasheet.co.kr datasheet pdf - http://www..net/
- 41 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 5.1 wp ac timing guide enabling wp during erase and program busy is prohibited. the erase and program operations ar e enabled and disabled as follows: figure 18. program operation 1. enable mode | 80h 10h we i/o wp r/b tww(min.100ns) 2. disable mode | 80h 10h we i/o wp r/b tww(min.100ns) figure 19. erase operation 1. enable mode 60h d0h we i/o wp r/b tww(min.100ns) 2. disable mode 60h d0h we i/o wp r/b tww(min.100ns) | | www.datasheet.co.kr datasheet pdf - http://www..net/
- 42 - datasheet mcp memory rev. 0.0 preliminary K521F12ACD-B060 512mb (32m x16) m-ddr sdram i-die www.datasheet.co.kr datasheet pdf - http://www..net/
- 43 - datasheet mcp memory rev. 0.0 preliminary K521F12ACD-B060 1.0 functional description figure 1. state diagram read self refresh auto refresh power down row active reada writea writea precharge preall idle power down refs refsx refa mrs ckel ckeh act ckeh ckel write write writea reada pre pre reada reada read read automatic sequence command sequence writea burst stop self refresh partial pre mrs emrs all banks precharge on power power applied all banks precharged pre www.datasheet.co.kr datasheet pdf - http://www..net/
- 44 - datasheet mcp memory rev. 0.0 preliminary K521F12ACD-B060 2.0 mode register definition 2.1 mode register set(mrs) the mode register is designed to support the va rious operating modes of mobile ddr sdra m. it includes cas latency, addressing m ode, burst length, test mode and vendor specific options to make mobile ddr sdram us eful for variety of applications . the mode register is written by asserting low on cs , ras , cas and we (the mobile ddr sdram should be in active m ode with cke already high prior to writing into the mode register). the states of address pins a0 ~ a12 and ba0, ba1 in the same cycle as cs , ras , cas and we going low are written in the mode register. two clock cycles are required to complete the write operation in the mode register. even if the power-up sequence is finished and some read or write operation is executed afterward, the mode register contents can be changed with the sa me command and two clock cycles. this command must be issued on ly when all banks are in the idle state. the mode register is divided into variou s fields depending on functionality. the burst length uses a0 ~ a2, addressing mode uses a3, cas latency(read latency from colu mn address) uses a4 ~ a6, a7 ~ a12 is used for test mode. ba0 and ba1 must be set to low fo r proper mrs opera- tion. figure 2. mode register set address bus a 2 a 1 a 0 burst type 0 0 0 reserved 001 2 010 4 011 8 100 16 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved a 3 burst type 0 sequential 1 interleave mode register ba1 ba0 a12 ~ a10/ap a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 bt burst length 0 rfu 1) 0 0 0 cas latency a6 a5 a4 cas latency 0 0 0 reserved 0 0 1 reserved 0 1 0 reserved 011 3 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved note : 1) rfu(reserved for future use) should stay "0" during mrs cycle www.datasheet.co.kr datasheet pdf - http://www..net/
- 45 - datasheet mcp memory rev. 0.0 preliminary K521F12ACD-B060 [table 1] burst address ordering for burst length burst length starting address (a3, a2, a1, a0) sequential mode interleave mode 2 xxx0 0, 1 0, 1 xxx1 1, 0 1, 0 4 xx00 0, 1, 2, 3 0, 1, 2, 3 xx01 1, 2, 3, 0 1, 0, 3, 2 xx10 2, 3, 0, 1 2, 3, 0, 1 xx11 3, 0, 1, 2 3, 2, 1, 0 8 x000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 x001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 x010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 x011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 x100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 x101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 x110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 x111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 16 0000 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15 0001 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11,10,13,12,15,14 0010 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1 2, 3, 0, 1, 6, 7, 4, 5,10,11, 8, 9, 14,15,12,13 0011 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4,11,10, 9, 8, 15,14,13,12 0100 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3,12,13,14,15, 8, 9, 10,11 0101 5, 6, 7,8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2,13,12,15,14, 9, 8,11,10 0110 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1,14,15,12,13,10,11, 8, 9 0111 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0, 15,14,13,12,11,10, 9, 8 1000 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5, 6, 7 8, 9,10,11,12,13,14,15, 0, 1, 2, 3, 4, 5, 6, 7 1001 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5, 6, 7, 8 9, 8, 11,10,13,12,15,14,1, 0, 3, 2, 5, 4, 7, 6 1010 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 10,11, 8, 9, 14,15,12,13, 2, 3, 0, 1, 6, 7, 4, 5 1011 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 11,10, 9, 8, 15,14,13,12, 3, 2, 1, 0, 7, 6, 5, 4 1100 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 12,13,14,15, 8, 9, 10,11, 4, 5, 6, 7, 0, 1, 2, 3 1101 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11,12 13,12,15,14, 9, 8,11,10, 5, 4, 7, 6, 1, 0, 3, 2 1110 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 14,15,12,13,10,11, 8, 9, 6, 7, 4, 5, 2, 3, 0, 1 1111 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 15,14,13,12,11,10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 www.datasheet.co.kr datasheet pdf - http://www..net/
- 46 - datasheet mcp memory rev. 0.0 preliminary K521F12ACD-B060 2.2 extended mode register set(emrs) the extended mode register is designed to support for the desired operating modes of ddr sdram. the extended mode register is w ritten by asserting low on cs , ras , cas , we and high on ba1 ,low on ba0(the mobile ddr sdram should be in all bank precharge with cke already high prior to writing into the extended mode register). the state of address pins a0 ~ a12 in the same cycle as cs , ras , cas and we going low is written in the extended mode register. two clock cycles are required to complete the write operation in the extended mode register. even if the power -up sequence is finished and some read or write operations is executed afterward, t he mode register contents can be changed with the same command and t wo clock cycles. but this command must be issued only when all banks are in the idle st ate. a0 - a2 are used for partial array self refresh and a5 - a6 are used for driver strength control. "high" on ba1 and"low" on ba0 are used for emrs . all the other address pins except a0,a1,a2,a5,a6, ba1, ba0 must be set to low for proper emrs operation. refer to the table for specific codes. figure 3. address bus ba1 ba0 a12 ~ a10/ap a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 mode register 1 pasr 0 rfu 1) 0 0 rfu 1) ds ds a 7 a 6 a 5 driver strength 000 full 001 1/2 010 1/4 011 1/8 100 3/4 101 3/8 110 5/8 111 7/8 pasr a 2 a 1 a 0 refreshed area 000 full array 001 1/2 array 010 1/4 array 011 reserved 100 reserved 101 reserved 110 reserved 111 reserved extended mode register set note : 1) rfu(reserved for future use) should stay "0" during emrs cycle www.datasheet.co.kr datasheet pdf - http://www..net/
- 47 - datasheet mcp memory rev. 0.0 preliminary K521F12ACD-B060 2.3 internal temperature compensated self refresh (tcsr) 1. in order to save power consumption, this mobile dram inclu des the internal temperature sens or and control units to control t he self refreshcycle auto- matically according to the real device temperature. 2. tcsr ranges for idd6 shown in the table are as an example only. max idd6 valus for 45 q c, 85 q c are guaranteed. typical values for 85 q c, 70 q c, 45 q c and 15 q c are obtained from dev ice characterization. 3. if the emrs for external tcsr is issued by th e controller, this emrs code for tcsr is ignored. 2.4 partial array self refresh (pasr) 1. in order to save power consumption, mobile ddr sdram includes pasr option. 2. mobile ddr sdram supports three kinds of pasr in self refresh mode; full array, 1/2 array, 1/4 array. figure 4. emrs code and tcsr , pasr - full array - 1/2 array - 1/4 array partial self refresh area ba1=0 ba0=0 ba1=0 ba0=1 ba1=1 ba0=1 ba1=1 ba0=0 ba1=0 ba0=0 ba1=0 ba0=1 ba1=1 ba0=1 ba1=1 ba0=0 ba1=0 ba0=0 ba1=0 ba0=1 ba1=1 ba0=1 ba1=1 ba0=0 temperature range self refresh current (idd6) unit full array 1/2 array 1/4 array typ. max typ. max typ. max 85 q c 400 500 300 400 250 350 ua 70 q c 250 200 165 45 q c 150 250 120 220 100 200 15 q c 140 110 95 www.datasheet.co.kr datasheet pdf - http://www..net/
- 48 - datasheet mcp memory rev. 0.0 preliminary K521F12ACD-B060 3.0 absolute maximum ratings note : 1) permanent device damage may occur if absolute maximum ratings are exceeded. 2) functional operation should be restricted to recommend operation condition. 3) exposure to higher than recommended voltage for exte nded periods of time could affect device reliability. 4.0 dc operating conditions recommended operating conditions(voltage referenced to vss=0v, tc = -25 c to 85 c) note : 1) under all conditions, vddq must be less than or equal to vdd. 2) these parameters should be tested at th e pin on actual components and may be checked at either the pin or the pad in simulat ion. 3) any input 0v vin vddq. input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs. parameter symbol value unit voltage on any pin relative to v ss v in , v out -0.5 ~ 2.7 v voltage on v dd supply relative to v ss v dd -0.5 ~ 2.7 v voltage on v ddq supply relative to v ss v ddq -0.5 ~ 2.7 v storage temperature t stg -55 ~ +150 c power dissipation p d 1.0 w short circuit current i os 50 ma parameter symbol min max unit note supply voltage(for device with a nominal vdd of 1.8v) vdd 1.7 1.95 v 1 i/o supply voltage vddq 1.7 1.95 v 1 input logic high voltage ( for add.) vih(dc) 0.8 x vddq vddq+0.3 v 2 input logic high voltage (for data) 0.7 x vddq vddq+0.3 v input logic low voltage ( for add.) vil(dc) -0.3 0.2 x vddq v 2 input logic low voltage (for data) -0.3 0.3 x vddq v output logic high voltage voh(dc) 0.9 x vddq - v ioh = -0.1ma output logic low voltage vol(dc) - 0.1 x vddq v iol = 0.1ma input leakage current ii -2 2 ua 3 output leakage current ioz -5 5 ua www.datasheet.co.kr datasheet pdf - http://www..net/
- 49 - datasheet mcp memory rev. 0.0 preliminary K521F12ACD-B060 5.0 dc characteristics recommended operating conditions (voltage referenced to v ss = 0v, tc = -25 to 85 c) note : 1) idd5 is measured in the below test condition. 2) the idd values need to be measured after devices are proper ly initialized following all sequences including mrs and emrs in "power up sequence" section in the specifi- cation. 3) input slew rate is 1v/ns. 4) definitions for idd: low is defined as v in 0.1 * vddq ; high is defined as v in 0.9 * vddq ; stable is defined as inputs stable at a high or low level ; switching is defined as: - address and command: inputs changing between high and low once per two clock cycles ; - data bus inputs: dq changing between high an d low once per clock cycle; dm and dqs are stable. 5) dpd(deep power down) function is an optional feature, and it will be enabled upon request. please contact samsung for more information. parameter symbol test condition 333mbps@cl3 unit note operating current (one bank active) idd0 trc=trcmin; tck=tckmin; cke is high; cs is high between valid commands; address inputs are switching; data bus inputs are stable 50 ma precharge standby current in power-down mode idd2p all banks idle, cke is low; cs is high, tck = tckmin; address and control inputs are switching; data bus inputs are stable 0.3 ma idd2ps all banks idle, cke is low; cs is high, ck = low, ck = high; address and control inputs are switching; data bus inputs are stable 0.3 precharge standby current in non power-down mode idd2n all banks idle, cke is high; cs is high, tck = tckmin; address and control inputs are switching; data bus inputs are stable 10 ma idd2ns all banks idle, cke is high; cs is high, ck = low, ck = high; address and control inputs are switching; data bus inputs are stable 4 active standby current in power-down mode idd3p one bank active, cke is low; cs is high, tck = tckmin; address and control inputs are switching; data bus inputs are stable 3 ma idd3ps one bank active, cke is low; cs is high, ck = low, ck = high; address and control inputs are switching; data bus inputs are stable 2 active standby current in non power-down mode (one bank active) idd3n one bank active, cke is high; cs is high, tck = tckmin; address and control inputs are switching; data bus inputs are stable 12 ma idd3ns one bank active, cke is high; cs is high, ck = low, ck = high; address and control inputs are switching; data bus inputs are stable 8 operating current (burst mode) idd4r one bank active; bl=4; cl=3; tck = tckmin; continuous read bursts; i out =0 ma address inputs are switching; 50% data change each burst transfer 80 ma idd4w one bank active; bl = 4; tck = tckmin ; continuous write bursts; address inputs are switching; 50% data change each burst transfer 70 refresh current idd5 trc trfc; tck = tckmin ; burst refresh; cke is high; address and control inputs are switching; data bus inputs are stable 80 ma 1 self refresh current idd6 cke is low; t ck = t ckmin ; extended mode register set to all 0?s; address and control inputs are stable; data bus inputs are stable tcsr range values typ max full array 85 c 400 500 ua 70 c 250 45 c 150 250 15 c 140 1/2 array 85 c 300 400 ua 70 c 200 45 c 120 220 15 c 110 1/4 array 85 c 250 350 ua 70 c 165 45 c 100 200 15 c 95 density 128mb 256mb 512mb 1gb 2gb unit trfc 80 80 110 140 140 ns www.datasheet.co.kr datasheet pdf - http://www..net/
- 50 - datasheet mcp memory rev. 0.0 preliminary K521F12ACD-B060 6.0 ac operating conditions & timming specification note : 1) these parameters should be tested at th e pin on actual components and may be checked at either the pin or the pad in simulat ion. 2) the value of v ix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the same. parameter/condition symbol min max unit note input high (logic 1) voltage, all inputs v ih (ac) 0.8 x vddq vddq+0.3 v 1 input low (logic 0) voltage, all inputs v il (ac) -0.3 0.2 x vddq v 1 input crossing point voltage, ck and ck inputs v ix (ac) 0.4 x vddq 0.6 x vddq v 2 www.datasheet.co.kr datasheet pdf - http://www..net/
- 51 - datasheet mcp memory rev. 0.0 preliminary K521F12ACD-B060 7.0 ac timming parameters & specifications parameter symbol 333mbps@cl3 unit note min max clock cycle time cl=3 tck 6 ns 1,2 row cycle time trc 60 ns row active time tras 42 70,000 ns ras to cas delay trcd 18 ns row precharge time trp 18 ns row active to row active delay trrd 12 ns write recovery time twr 12 ns last data in to active delay tdal - - 3 last data in to read command tcdlr 1 tck col. address to col. address delay tccd 1 tck clock high level width tch 0.45 0.55 tck clock low level width tcl 0.45 0.55 tck dq output data access time from ck/ck cl=3 tac 2 5.5 ns 4 dqs output data access time from ck/ck cl=3 tdqsck 2 5.5 ns data strobe edge to ouput data edge tdqsq 0.5 ns read preamble cl=3 trpre 0.9 1.1 tck read postamble trpst 0.4 0.6 tck ck to valid dqs-in tdqss 0.75 1.25 tck dqs-in setup time twpres 0 ns 5 dqs-in hold time twpreh 0.25 tck dqs-in high level width tdqsh 0.4 0.6 tck dqs-in low level width tdqsl 0.4 0.6 tck dqs falling edge to ck setup time tdss 0.2 tck dqs falling edge hold time from ck tdsh 0.2 tck dqs-in cycle time tdsc 0.9 1.1 tck address and control input setup time fast slew rate tis 1.1 ns 7 slow slew rate 8 address and control input hold time fast slew rate tih 1.1 ns 7 slow slew rate 8 address & control input pulse width tipw 2.2 dq & dm setup time to dqs fast slew rate tds 0.6 ns 6,7 slow slew rate 6,8 dq & dm hold time to dqs fast slew rate tdh 0.6 ns 6,7 slow slew rate 6,8 dq & dm input pulse width tdipw 1.2 ns dq & dqs low-impedence time from ck/ck tlz 1.0 ns dq & dqs high-impedence time from ck/ck thz 5.5 ns dqs write postamble time twpst 0.4 0.6 tck dqs write preamble time twpre 0.25 tck refresh interval time tref 64 ms mode register set cycle time tmrd 2 tck power down exit time tpdex 1 tck www.datasheet.co.kr datasheet pdf - http://www..net/
- 52 - datasheet mcp memory rev. 0.0 preliminary K521F12ACD-B060 note : 1) tck(max) value is measured at 100ns. 2) the only time that the clock frequency is allowed to be changed is during clock stop, power-down, self-refresh modes. 3) in case of below 33mhz (tck=30ns) c ondition, sec could support tdal(=2*tck). tdal =(twr/tck) + (trp/tck) 4) tac(min) value is measured at the high vdd(1.95v) and cold temperature(-25 c). tac(max) value is measured at the low vdd(1.7v) and hot temperature(85 c). tac is measured in the device with half driver streng th and under the ac output load condition (fig.6 in next page). 5) the specific requirement is that dqs be valid(high or low) on or before this ck edge. the case shown(dqs going from high_z t o logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high at this time, depend ing on tdqss. 6) i/o delta rise/fall ra te(1/slew-rate) derating this derating table is used to increase tds/tdh in the case where the dq and dqs slew rates differ. the delta rise/fall rate is calculated as 1/slewrate1-1/slewrate2. for example, if slew rate 1 = 1.0v/ns and slew rate 2 =0.8v/ns, then the delta rise/fall rate =-0.25ns/v. 7) input slew rate 1.0 v/ ns. 8) input slew rate 0.5v/ns and < 1.0v/ns. 9) maximum burst refresh cycle : 8 parameter symbol 333mbps@cl3 unit note min max cke min. pulse width(high and low pulse width) tcke 2 tck auto refresh cycle time trfc 72 ns 9 exit self refresh to active command txsr 120 ns data hold from dqs to earliest dq edge tqh thpmin- tqhs ns data hold skew factor tqhs 0.65 ns clock half period thp tclmin or tchmin ns data rise/fall rate ? tds ? tdh (ns/v) (ps) (ps) 000 0.25 +50 +50 0.5 +100 +100 www.datasheet.co.kr datasheet pdf - http://www..net/
- 53 - datasheet mcp memory rev. 0.0 preliminary K521F12ACD-B060 8.0 ac operating test conditions (vdd = 1. 7 v to 1.95 v, tc = -25 c to 85 c) figure 5. dc output load circuit figure 6. ac output load circuit 1), 2) note : 1) the circuit shown above repr esents the timing reference load used in defin ing the relevant timing parameters of the part. it is not intended to be either a precise representa- tion of the typical system environment nor a depiction of the ac tual load presented by a production tester. system designers wi ll used ibis or other simulations tools to correlate the timing reference load to system environment. manufacturers wil l correlate to their poduction test conditions (generally a c oaxial transmission line terminated at the tester electronics). for the half strength driver with a nominal 10pf lo ad parameters tac and tqh are expected to be in ther same rang e. however, these parameters are not subject to production test but are estimated by design / characterization. use of ibis or other simulation tolls for system design vali dation is suggested. 2) based on nominal impedance at 0.5 x vddq. the impedence for half(1/2) driver strength is designed 55ohm. and for other driver strength, it is designed proportionally. parameter value unit ac input levels (vih/vil) 0.8 x vddq / 0.2 x vddq v input timing measurement reference level 0.5 x vddq v input signal minimum slew rate 1.0 v/ns output timing measurement reference level 0.5 x vddq v output load condition see figure 6 1.8v 13.9k ? 10.6k ? output 20pf - voh (dc) = 0.9 x vddq, ioh = -0.1ma - vol (dc) = 0.1 x vddq, iol = 0.1ma vtt=0.5 x v ddq 50 ? output z0=50 ? test load values need to be proportional to the driver strength which is set by the controller. - test load for full driver strength buffer (20pf) - test load for half driver strength buffer (10pf) www.datasheet.co.kr datasheet pdf - http://www..net/
- 54 - datasheet mcp memory rev. 0.0 preliminary K521F12ACD-B060 9.0 input/output capacitance (vdd=1.8, vddq=1.8v, tc = 25 c, f=100mhz) parameter symbol min max unit input capacitance (a0 ~ a12, ba0 ~ ba1, cke, cs , ras ,cas , we ) cin1 1.5 3.0 pf input capacitance( ck, ck ) cin2 1.5 3.5 pf data & dqs input/output capacitance cout 2.0 4.5 pf input capacitance(dm) cin3 2.0 4.5 pf www.datasheet.co.kr datasheet pdf - http://www..net/
- 55 - datasheet mcp memory rev. 0.0 preliminary K521F12ACD-B060 10.0 ac overshoot/undershoot specification for address & control pins figure 7. ac overshoot and undershoot definition for address and control pins 11.0 ac overshoot/undershoot specification for clk, dq, dqs and dm pins figure 8. ac overshoot and undershoot definition for clk, dq, dqs and dm pins parameter specification maximum peak amplitude allowed for overshoot area 0.9v maximum peak amplitude allowed for undershoot area 0.9v maximum overshoot area above vdd 3v-ns maximum undershoot area below vss 3v-ns parameter specification maximum peak amplitude allowed for overshoot area 0.9v maximum peak amplitude allowed for undershoot area 0.9v maximum overshoot area above vddq 3v-ns maximum undershoot area below vssq 3v-ns overshoot area maximum amplitude vdd undershoot area maximum amplitude vss volts (v) time (ns) overshoot area maximum amplitude vddq undershoot area maximum amplitude vssq volts (v) time (ns) www.datasheet.co.kr datasheet pdf - http://www..net/
- 56 - datasheet mcp memory rev. 0.0 preliminary K521F12ACD-B060 12.0 command truth table (v=valid, x=don?t care, h=logic high, l=logic low) note : 1) op code : operand code. a0 ~ a12 & ba0 ~ ba1 : program keys. (@emrs/mrs) 2) emrs/ mrs can be issued only at all banks precharge state. a new command can be issued 2 clock cycles after emrs or mrs. 3) auto refresh functions are same as the cbr refresh of dram. the automatical precharge without row precharge command is meant by "auto". auto/self refresh can be issued only at all banks precharge state. 4) ba0 ~ ba1 : bank select addresses. 5) if a10/ap is "high" at row precharge, ba0 and ba1 are ignored and all banks are selected. 6) during burst write with auto precharge, new read/write command can not be issued. another bank read/write command can be issued after the end of burst. new row active of the associated bank can be issued at trp after the end of burst. 7) burst stop command is valid at every burst length. 8) dm sampled at the rising and falling edges of the dqs and data -in are masked at the both edges (write dm latency is 0). 9) this combination is not defined for any function, which means "no operation(nop)" in mobile ddr sdram. command cken-1 cken cs ras cas we ba0,1 a10/ap a12,a11, a9~a0 note register mode register set h x l l l l op code 1, 2 refresh auto refresh h h ll lh x 3 self refresh entry l 3 exit l h lh hh x 3 hx x x 3 bank active & row addr. h x l l h h v row address read & column address auto precharge disable hxlhlhv l column address (a0~a9) 4 auto precharge enable h4 write & column address auto precharge disable hxlhllv l column address (a0~a9) 4 auto precharge enable h4, 6 burst stop h x l h h l x 7 precharge bank selection hxllhl vl x all banks x h 5 active power down entry h l hx x x x lh hh exit l h x x x x precharge power down entry h l hx x x x lh hh exit l h hx x x lh hh dm h x x 8 no operation (nop) : not defined h x hx x x x 9 lh hh 9 www.datasheet.co.kr datasheet pdf - http://www..net/
- 57 - datasheet mcp memory rev. 0.0 preliminary K521F12ACD-B060 13.0 functional truth table current state cs ras cas we address command action precharge standby l h h l x burst stop illegal 2) l h l x ba, ca, a10 read/write illegal 2) l l h h ba, ra active bank active, latch ra l l h l ba, a10 pre/prea illegal 4) lllhx refresh auto-refresh 5) llllop-c ode, mode-add mrs mode register set 5) active standby l h h l x burst stop nop l h l h ba, ca, a10 read/reada begin read, latch ca, determine auto-precharge l h l l ba, ca, a10 write/writea begin write, latch ca, determine auto-precharge l l h h ba, ra active bank active/illegal 2) l l h l ba, a10 pre/prea precharge/precharge all l l l h x refresh illegal llllop-c ode, mode-add mrs illegal read l h h l x burst stop terminate burst l h l h ba, ca, a10 read/reada terminate burst, latch ca, begin new read, determine auto-precharge 3) l h l l ba, ca, a10 write/writea illegal l l h h ba, ra active bank active/illegal 2) l l h l ba, a10 pre/prea terminate burst, precharge 10) l l l h x refresh illegal llllop-c ode, mode-add mrs illegal write l h h l x burst stop illegal l h l h ba, ca, a10 read/reada terminate burst with dm=high, latch ca, begin read, determine auto-precharge 3) l h l l ba, ca, a10 write/writea terminate burst, latch ca, begin new write, determine auto- precharge 3) l l h h ba, ra active bank active/illegal 2) l l h l ba, a10 pre/prea terminate burst with dm=high, precharge 10) l l l h x refresh illegal llllop-c ode, mode-add mrs illegal read with auto precharge 6) (reada) l h h l x burst stop illegal l h l h ba, ca, a10 read/reada 6) l h l l ba, ca, a10 write/writea illegal l l h h ba, ra active 6) l l h l ba, a10 pre/prea 6) l l l h x refresh illegal llllop-c ode, mode-add mrs illegal www.datasheet.co.kr datasheet pdf - http://www..net/
- 58 - datasheet mcp memory rev. 0.0 preliminary K521F12ACD-B060 current state cs ras cas we address command action write with auto recharge 7) (writea) l h h l x burst stop illegal l h l h ba, ca, a10 read/reada 7) l h l l ba, ca, a10 write/writea 7) l l h h ba, ra active 7) l l h l ba, a10 pre/prea 7) lllhx refresh illegal l l l l op-code, mode-add mrs illegal precharging (during trp) lhhlx burst stop illegal 2) l h l x ba, ca, a10 read/write illegal 2) l l h h ba, ra active illegal 2) l l h l ba, a10 pre/prea nop 4) (idle after trp) lllhx refresh illegal l l l l op-code, mode-add mrs illegal row activating (from row active to trcd) lhhlx burst stop illegal 2) l h l x ba, ca, a10 read/write illegal 2) l l h h ba, ra active illegal 2) llhl ba, a10 pre/prea illegal 2) lllhx refresh illegal l l l l op-code, mode-add mrs illegal write recovering (during twr or tcdlr) lhhlx burst stop illegal 2) l h l h ba, ca, a10 read illegal 2) l h l l ba, ca, a10 write write l l h h ba, ra active illegal 2) l l h l ba, a10 pre/prea illegal 2) lllhx refresh illegal l l l l op-code, mode-add mrs illegal re- freshing l h h l x burst stop illegal l h l x ba, ca, a10 read/write illegal l l h h ba, ra active illegal l l h l ba, a10 pre/prea illegal lllhx refresh illegal l l l l op-code, mode-add mrs illegal mode register setting l h h l x burst stop illegal l h l x ba, ca, a10 read/write illegal l l h h ba, ra active illegal llhl ba, a10 pre/prea illegal lllhx refresh illegal l l l l op-code, mode-add mrs illegal www.datasheet.co.kr datasheet pdf - http://www..net/
- 59 - datasheet mcp memory rev. 0.0 preliminary K521F12ACD-B060 (h=high level, l=low level, x=don t care) note : 1) all entries assume that cke was high during the preceding clock cycle and the current clock cycle. 2) illegal to bank in specified state ; function may be legal in the bank indicated by ba, depending on the state of that bank. (illegal = device operation and/or data integrity are not guaranteed.) 3) must satisfy bus contention, bus turn around and write recovery requirements. 4) nop to bank precharging or in idle sate. may precharge bank indicated by ba. 5) illegal if any bank is not idle. 6) refer to "read with auto precharge timing diagram" for detailed information. 7) refer to "write with auto precharge timing diagram" for detailed information. 8) cke low to high transition will re-enable ck, ck and other inputs asynchronously. a minimum setup time must be satisfied before issuing any command other than exit. 9) power-down, self-refresh can be entered only from all bank idle state. current state cke n-1 cke n cs ras cas we add action self- refreshing 8) l h h x x x x exit self-refresh lhlhhhxexit self-refresh lhlhhlxillegal lhlhlxxillegal l h l l x x x illegal l l x x x x x nop (maintain self-refresh) power down l h x x x x x exit power down(idle after tpdex) l lxxxxxnop (maintain power down) all banks idle 9) h h x x x x x refer to function truth table h l l l l h x enter self-refresh h l h x x x x enter power down h l l h h h x enter power down h l l h h l x illegal h l l h l x x illegal hlllxxxillegal l x x x x x x refer to current state=power down www.datasheet.co.kr datasheet pdf - http://www..net/
- 60 - - 60 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary device operations & timing diagram www.datasheet.co.kr datasheet pdf - http://www..net/
- 61 - - 61 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary device operations www.datasheet.co.kr datasheet pdf - http://www..net/
- 62 - - 62 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 1. precharge the precharge command is used to precharge or close a bank that has been activated. the precharge command is issued when cs , ras and we are low and cas is high at the rising edge of the clock. the precharge comm and can be used to precharge each ban k respectively or all banks s imulta- neously. the bank select addresses(ba0, ba1) are used to define which bank is prechar ged when the command is initiated. for wr ite cycle, twr(min.) must be satisfied until the precharge command can be issued. af ter trp from the precharge, an active command to the same bank can be initiated. table 1. bank selection for precharge by bank address bits 2. no operation(nop) & device deselect the device should be deselec ted by deactivating the cs signal. in this mode, mobile ddr sdram shoul d ignore all the control inputs. the mobile ddr sdram is put in nop mode when cs is activated and ras , cas and we are deactivated. both device deselect and nop command can not affect operation already in progress. so even if the device is deselected or nop command is issued under operation, the operation will be completed. a10/ap ba1 ba0 precharge 000 bank a only 001 bank b only 010 bank c only 011 bank d only 1 x x all banks www.datasheet.co.kr datasheet pdf - http://www..net/
- 63 - - 63 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 3. row active the bank activation command is issued by holding cas and we high with cs and ras low at the rising edge of the clock(ck). the mobile ddr sdram has four independent banks, so two bank select addresses(ba0, ba1 ) are required. the bank activation command must be applied be fore any read or write operation is executed. the delay from the bank activation command to the first read or write command must meet or exceed the minimum of ras to cas delay time, trcd(min). once a bank has been activated, it mu st be precharged before another bank activation command can be app lied to the same bank. the minimum time interval between interleaved bank activation commands(bank a to bank b and vice versa) is the bank to bank delay time, trrd(min). any system or application incorporating random access memory products should be prop erly designed, tested and qulifided to ensu re proper use or access of such memory products. disproportionate, excessive and/or repeated access to a particular address or addresses may res ult in reduction of product life. figure 1. bank activation command cycle timing address command ras -cas delay(trcd) bank a row addr. bank a col. addr. bank a activate write a with auto nop precharge ras -ras delay time(trrd) bank b row addr. bank a row. addr. bank b activate bank a activate nop row cycle time(trc) tn tn+1 tn+2 2 0 1 : don c t care ck ck 5 3 4 nop nop nop 4. read bank this command is used after the row activate command to initiate t he burst read of data. the read command is initiated by activa ting ras , cs , cas , and we at the same clock sampling(rising) edge as described in the command truth table. the length of the burst and the cas latency t ime will be determined by the values programmed during the mrs cycle. 5. write bank this command is used after the row activate command to initiate the burst write of data. the write command is initiated by acti vating ras , cs , cas , and we at the same clock sampling(rising) edge as described in the command truth table. the length of the burst will be determined b y the values pro- grammed during the mrs cycle. www.datasheet.co.kr datasheet pdf - http://www..net/
- 64 - - 64 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 6. burst read operation burst read operation in mobile ddr sdram is in the same manner as the mobile sdr sdram such that the burst read command is issu ed by asserting cs and cas low while holding ras and we high at the rising edge of the clock(ck) after trcd from the bank activation. the address inputs determine the starting address for the burst. the mode register sets type of burst(sequential or interleave) and burst length(2, 4, 8, 16 ). the first output data is available with a cas latency from the read command, and the consecutive data are presented on the falling and rising edge of d ata strobe(dqs) adopted by mobile ddr sdram until the burst length is completed. figure 2. burst read operation timing command read a nop nop nop nop nop nop nop nop 2 01 5 34 8 67 dqs dqs dout 0 dout 1 dout 2 dout 3 t rpst t rpre preamble postamble ck ck t dqsck t ac hi-z hi-z note : 1) burst length=4, cas latency= 3 www.datasheet.co.kr datasheet pdf - http://www..net/
- 65 - - 65 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 7. burst write operation the burst write command is issued by having cs , cas , and we low while holding ras high at the rising edge of the clock(ck). the address inputs determine the starting column address. there is no write latency relative to dqs requi red for burst write cycle. the first data of a burst write cycle must be applied on the dq pins tds(data-in setup time) prior to data strobe edge enabled after tdqss from the rising edge of the clock( ck) that the write com- mand is issued. the remaining data inputs must be supplied on each subsequent falling and rising edge of data strobe until the burst length is com- pleted. when the burst has been finished, any additi onal data supplied to the dq pins will be ignored. figure 3. command twr twr t dqss(min) t dqss(max) 2 01 5 34 8 67 t wpres t wpreh t wpres t wpreh ck ck din 3 din 0 din 1 din 2 din 3 din 0 din 1 din 2 din 3 din 0 din 1 din 2 din 3 din 0 din 1 din 2 nop writea nop nop nop writeb nop nop nop t ds t dh hi-z hi-z hi-z hi-z tdqss(max) tdqss(min) dqs dqs dqs dqs burst write operation timing note : 1) burst length=4 2) the specific requirement is that dqs be valid(high or low) on or before this ck edge. the case shown (dqs going from high_z to logic low) applies when no writes were pr eviously in pr ogress on the bus. www.datasheet.co.kr datasheet pdf - http://www..net/
- 66 - - 66 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 8. read interrupted by a read a burst read can be interrupted by new read command of any bank befor e completion of the burst. when the previous burst is inte rrupted, the new address with the full burst length override the remaining address. the data from the first read command continues to appear on the outputs until the cas latency from the interrupting read command is satisfied. at th is point, the data from the interrupting read command appears. r ead to read interval is minimum 1 clock. figure 4. command read read nop nop nop nop nop nop nop dqs dqs dout a 0 dout a 1 dout b 0 dout b 1 dout b 2 dout b 3 ck 2 01 5 34 8 67 t rpre preamble t dqsck ck ck ck t ccd(min) t rpst hi-z hi-z read interrupted by a read timing note : 1) burst length=4, cas latency=3 9. read interrupted by a write & burst stop to interrupt a burst read with a write command, burst stop comm and must be asserted to avoid data contention on the i/o bus by placing the dqs(output drivers) in a high impedance state. figure 5. command read burst stop nop write nop nop nop dqs dqs dout 0 dout 1 din 0 din 1 din 2 din 3 2 01 5 34 8 67 nop t wpreh t wpres t rpre t dqss t dqsck t ac ck ck nop t wpst hi-z hi-z t wpre t rpst read interrupted by a write and burst stop timing. note : 1) burst length=4, cas latency=3 the following functionality establishes how a write command may interrupt a burst read. 1. for write commands interrupting a burst read, a burst termi nate command is required to stop the burst read and tri-state the dq bus prior to valid input write data. burst stop command must be applied at least 2 cloc k cycles for cl=2 and at leas t 3 clock cycles for cl=3 befo re the write command. 2. it is illegal for a write command to interrupt a read with autoprecharge command. www.datasheet.co.kr datasheet pdf - http://www..net/
- 67 - - 67 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 10. read interrupted by a precharge a burst read operation can be interrupted by precharge of the same bank. the minimum 1 clock is required for the read to precha rge intervals. the latency from a precharge command to invalid out put is equivalent to the cas latency. figure 6. command read nop precharge nop nop nop nop nop nop dqs dqs dout 0 dout 1 dout 2 dout 3 interrupted by precharge 2 01 5 34 8 67 dout 4 dout 5 dout 6 dout 7 1tck t rpre t dqsck t ac ck ck hi-z hi-z read interrupted by a precharge timing note : 1) burst length=8, cas latency=3 when a burst read command is issued to a mobile ddr sdram, a prec harge command may be issued to the same bank before the read b urst is completed. the following functionality determines when a prec harge command may be given during a read burst and when a new ban k activate command may be issued to the same bank. 1. for the earliest possible precharge co mmand without interrupting a burst read, the precharge command may be given on the ris ing clock edge which is cl clock cycles before the end of the read burst where cl is the cas latency. a new bank activate command may be issued to the same bank after trp (row precharge time). 2. when a precharge command interrupts a burst read operation, the precharge command given on a rising clock edge terminates th e burst with the last valid data word presented on dq pins at cl-1(cl=cas laten cy) clock cycles after the command has been issued. once the las t data word has been output, the output buffers are tri-stated. a new bank activate command may be issued to the same bank after trp. 3. for a read with autoprecharge command, a new bank activate co mmand may be issued to the same bank after trp from rising cloc k that comes cl(cl=cas latency) clock cycles before the end of the read burst. during read with autoprecharge, the initiation of the intern al precharge occurs at the same time as the earliest possible external precharge command would initia te a precharge operation without interrupting the read burst as described in 1 above. 4. for all cases above, trp is an analog delay that needs to be co nverted into clock cycles. th e number of clock cycles betwee n a precharge command and a new bank activate command to the same bank equals trp/tck (w here tck is the clo ck cycle time) with the result rounded up to the nearest integer number of clock cycles. (note that rounding to x.5 is not possible since th e precharge and bank activate commands can only be given on a rising clock edge).in all cases, a precha rge operation cannot be initiated unless tras(mi n) [minimum bank activate to precharge time] has been satisfied. this includes read with autoprec harge commands where tras(min) must still be satisfied such that a read with autopr echarge command has the same timing as a read command followed by the earliest pos sible precharge command which does not interrupt the burst. www.datasheet.co.kr datasheet pdf - http://www..net/
- 68 - - 68 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 11. write interrupted by a write a burst write can be interrupted by a new write command before completion of the burst, where the interval between the successi ve write commands must be at least one clock cycle(tccd(min)). when the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied. figure 7. command nop write a write b nop nop nop nop nop nop dqs dqs din a 0 din a 1 din b 0 din b 1 din b 2 din b 3 tccd(min) 2 01 5 34 8 67 ck ck hi-z hi-z write interrupted by a write timing note : 1) burst length=4 www.datasheet.co.kr datasheet pdf - http://www..net/
- 69 - - 69 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 12. write interrupted by a precharge & dm a burst write operation can be interrupted by a precharge of the same bank before completion of the burst. random column access is allowed. a write recovery time(twr) is required from the last data to precharge command. when precharge command is asserted, any residual data f rom the burst write cycle must be masked by dm. figure 8. dina 2 dina 3 command nop write a nop nop prechargea nop nop write b dqs dqs dina 0 dina 1 dina 4 dina 5 dinb 0 dinb 1 dina 6 dina 7 twr dqs dqs twr t dqss(min) dina 0 dina 1 dina 2 dina 3 dina 4 dina 5 dina 6 dina 7 dm dinb 0 dinb 1 t dqss(max) 2 01 5 34 8 67 dm t wpres t wpreh t wpres t wpreh nop t dqss(max) t wpres t wpreh t dqss(min) t wpres t wpreh dinb 2 ck ck tdqss(max) tdqss(min) hi-z hi-z hi-z hi-z write interrupted by a precharge and dm timing note : 1) burst length=8 precharge timing for write operations in mobi le ddr sdram requires enough time to allow ?? write recovery?? which is the time re quired by a mobile ddr sdram core to properly store a full ??0?? or ??1?? level befor e a precharge operation. for mobile ddr sdram, a timing parameter , twr, is used to indicate the required amount of time between the last valid write operation and a precharge command to the same bank. the precharge timing for writes is a comple x definition since the write data is sampled by the data strobe and the address is s ampled by the input clock. inside the mobile ddr sdram, the data path is eventually synchronized wi th the address path by switching clock domains from the data strobe clock domain to the input clock domain. this makes the definition of when a precharge operation can be initiated after a write very complex since the write recovery parameter must make reference to only the clock domain that affects internal write operation, i.e., the input clock do main. twr starts on the rising clock edge after the last possible dq s edge that strobed in the last valid data and ends on the rising clock edge that strobes in the precharge command. 1. for the earliest possible precharge command following a burst write without interrupting the burst, the minimum time for wri te recovery is defined by twr. 2. when a precharge command interrupts a write burst operation, the data mask pin, dm, is used to mask input data during the ti me between the last valid write data and the rising clock edge on which the precharge comma nd is given. during this time, the dqs input is still r equired to strobe in the state of dm. the minimum time for write recovery is defined by twr. 3. for a write with autoprecharge command, a new bank activate co mmand may be issued to the same bank after twr+trp where twr+t rp starts on the falling dqs edge that strobed in the last valid data and ends on the rising clock edge that strobes in the bank activate co mmand. during write with autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible external precharg e command without interrupting the write burst as described in 1 above. 4. in all cases, a precharge operation cannot be initiated unless tras(min) [minimum bank activa te to precharge time] has been satisfied. this includes write with autoprecharge commands where tras(min) must still be satisfied such that a write with autoprecharge command has the same timing as a write command followed by the earliest possible precharge command which does not interrupt the burst. www.datasheet.co.kr datasheet pdf - http://www..net/
- 70 - - 70 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 13. write interrupted by a read & dm a burst write can be interrupted by a read command of any bank. t he dq?s must be in the high impedance state at least one clock cycle before the inter- rupting read data appear on the outputs to avoid data contenti on. when the read command is registered, any residual data from the burst write cycle must be masked by dm. the delay from the last data to read co mmand (tcdlr) is required to avoid the data contention mobile ddr sdram inside. data that are presented on the dq pins before the read command is init iated will actually be written to the memory. read command int errupting write can not be issued at the next clock edge of that of write command. figure 9. command nop write nop nop read nop nop nop nop din 0 din 1 din 2 din 3 din 4 din 5 din 6 din 7 tcdlr tdqss(max) tcdlr tdqss(min) din 7 din 0 din 1 din 2 din 3 din 4 din 5 din 6 2 0 1 5 3 4 8 6 7 twpres 5) ck ck dqs dqs dqs dqs dm dm tdqss(max) tdqss(min) nop dout0 dout1 dout2 dout3 hi-z hi-z hi-z hi-z dout0 dout1 dout2 dout3 9 dout4 dout4 nop twpres 5) write interrupted by a read and dm timing note : 1) burst length=8, cas latency=3 the following function establis hed how a read command may interrupt a write burst and which input data is not written into the memory. 1. for read commands interrupting a burst write, the minimum writ e to read command delay is 2 clock cycles. the case where the write to read delay is 1 clock cycle is disallowed. 2. for read commands interrupting a burst write, the dm pin must be used to mask the input data words whcich immediately preced e the interrupting read operation and the input data word which immediately follows the interrupting read operation 3. for all cases of a read interrupting a write, the dq and dqs bus es must be released by the driving chip (i.e., the memory co ntroller) in time to allow the buses to turn around before the mobile d dr sdram drives them during a read operation. 4. if input write data is masked by the read command, the dqs input is ignored by the mobile ddr sdram. 5. refer to burst write operation. www.datasheet.co.kr datasheet pdf - http://www..net/
- 71 - - 71 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 14. burst stop the burst stop command is initiated by having ras and cas high with cs and we low at the rising edge of the clock(ck). the burst stop command has the fewest restrictions making it the easiest method to use when terminating a burst read operation before it has been complete d. when the burst stop command is issued during a burst read cycle, the pair of data and dqs(data strobe) go to a high impedance state after a delay w hich is equal to the cas latency set in the mode register. however, the burst st op command is not supported during a burst write operation. figure 10. command read a burst stop nop nop nop nop nop nop nop dqs dqs dout 0 dout 1 2 01 5 34 8 67 the burst read ends after a delay equal to the cas latency. ck ck hi-z hi-z burst stop timing note : 1) burst length=4, cas latency= 3 the burst stop command is a mandatory feature for mobile ddr sdram. the following functionality is required: 1. the burst stop command may only be issued on the rising edge of the input clock, ck. 2. burst stop is only a valid command during read bursts. 3. burst stop during a write burst is undefined and shall not be used. 4. burst stop applies to all burst lengths. 5. burst stop is an undefined command during read with autoprecharge and shall not be used. 6. when terminating a burst read command, the bst command must be issued l bst (?bst latency?) clock cy cles before the clock edge at which the output buffers are tristated, where l bst equals the cas latency for read operations. 7. when the burst terminates, the dq and dqs pins are tristated. the burst stop command is not byte controllable and applies to all bits in the dq data word and the(all) dqs pin(s). www.datasheet.co.kr datasheet pdf - http://www..net/
- 72 - - 72 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 15. dm masking the mobile ddr sdram has a data mask function that can be used in conjunction with data write cy cle, not read cycle. when the d ata mask is acti- vated(dm high) during write operation, mobi le ddr sdram does not accept the corresponding data.(dm to data-mask latency is zer o). dm must be issued at the rising or falling edge of data strobe. figure 11. command write nop nop nop nop nop nop nop nop dqs dqs din 0 din 1 din 2 din 3 dm din 4 din 5 din 6 din7 masked by dm=h 2 01 5 34 8 67 t dqss t wpres t wpreh ck ck hi-z hi-z dm masking timing note : 1) burst length=8 www.datasheet.co.kr datasheet pdf - http://www..net/
- 73 - - 73 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 16. read with auto precharge if a10/ap is high when read command is issued , the read with auto-precharge function is performed. if a read with auto-prechar ge command is issued, the mobile ddr sdram automatically enters the precharge operation bl/2 clock later from a read with auto-precharge command when tras(min) is sat- isfied. if not, the start point of precharge operation will be delayed until tras(min) is satisf ied. once the precharge operat ion has started, the bank cannot be reactivated and the new command can not be assert ed until the precharge time(trp) has been satisfied. figure 12. read with auto precharge timing command bank a nop read a nop nop nop nop active auto precharge dqs dqs dout0 dout1 dout2 dout3 nop t rp bank can be reactivated at nop nop nop nop tras(min) auto-precharge starts ck ck completion of t rp 1) hi-z hi-z 2 01 5 34 8 67 91011 note : 1) burst length=4, cas latency= 3 2) the row active command of the precharge bank can be issued after trp from this point. note : 1) ap = auto precharge asserted command for same bank for different bank 5 6 7 5 6 7 read read +no ap 1) read+no ap illegal legal legal legal read+ap read + ap read + ap illegal legal legal legal active illegal illegal illegal legal legal legal precharge legal legal illegal legal legal legal www.datasheet.co.kr datasheet pdf - http://www..net/
- 74 - - 74 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 17. write with auto precharge if a10/ap is high when write command is issued , the write with auto-precharge function is performed. any new command to the sa me bank should not be issued until the internal precharge is completed. the internal precharge begins after keeping twr(min). figure 13. command bank a nop write a nop nop nop nop active auto precharge 2 01 5 34 8 67 dqs dqs din 0 din 1 din 2 din 3 nop t rp nop nop nop 91011 t wr internal precharge start 1) ck ck bank can be reactivated at completion of t rp hi-z hi-z nop nop nop 12 13 write with auto precharge timing note : 1) burst length=4 2) the row active command of the precharge bank can be issued after trp from this point. note : 1) ap = auto precharge 2) dm : refer to "27. write interrupted by precharge & dm ". asserted command for same bank for different bank 5 6 7 8 9 10 5 6 7 8 9 write write+ no ap 1) write+ no ap illegal illegal illegal illegal legal legal legal legal legal write+ ap write+ ap write+ ap illegal illegal illegal illegal legal legal legal legal legal read illegal read+ no ap+dm 2) read+ no ap+dm read+ no ap illegal illegal illegal illegal illegal legal legal read+ap illegal read + ap+dm read + ap+dm read + ap illegal illegal illegal illegal illegal legal legal active illegal illegal illegal ill egal illegal illegal legal legal legal legal legal precharge illegal illegal illegal il legal illegal illegal legal legal legal legal legal www.datasheet.co.kr datasheet pdf - http://www..net/
- 75 - - 75 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 18. auto refresh & self refresh 18.1. auto refresh an auto refresh command is issued by having cs , ras and cas held low with cke and we high at the rising edge of the clock(ck). all banks must be precharged and idle for trp(min) before the auto refresh command is applied. once this cycle has been started, no control of th e external address pins are required because of the internal addres s counter. when the refresh cycle has comp leted, all banks will be in the idle stat e. a delay between the auto refresh command and the next activate command or subsequent auto re fresh command must be greater than or equal to the trfc(min) . figure 14. auto refresh timing command cke pre t rp t rfc(min) auto = high refresh nop a a ck ck a a a a nop nop nop nop nop nop act a a dq high-z dqs high-z note : 1) trp=3clk 2) device must be in the all banks idle state prior to entering auto refresh mode. 18.2. self refresh a self refresh command is defined by having cs , ras , cas and cke held low with we high at the rising edge of the clock. once the self refresh com- mand is initiated, cke must be held low to keep the device in se lf refresh mode. after 1 clock cyc le from the self refresh comm and, all of the external control signals including system clock(ck, ck ) can be disabled except cke. the clock is internally di sabled during self refresh operation to reduce power. before returning cke high to exit the self refresh mode , apply stable clock input signal with deselect or nop command as serted. figure 15. command cke stable clock t is nop self refresh t xsr(min) t is a a a a a a active ck ck nop nop nop nop nop a a a a a a a a a a a a trfc dq high-z dqs high-z self refresh timing note : 1) device must be in the all banks idle state prior to entering self refresh mode. 2) the minimum time that the device must remain in self refresh mode si trfc. www.datasheet.co.kr datasheet pdf - http://www..net/
- 76 - - 76 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 19. power down the device enters power down mode when cke low,and it exits when cke high. once the power down mode is initiated, all of the re ceiver circuits except ck and cke are gated off to reduce power consumption. all banks should be in idle state prior to entering the precharge power down mode and cke should be set in high for at least tpdex prior to row acti ve command. refresh operations cannot be performed during power d own mode, therefore the device cannot remain in power down mode longer than the refresh period(tref) of the device. figure 16. power down entry and exit timing high-z cke precharge active power entry down precharge command t is t is t is t is a a a a a a a a a a a a a a a a power exit down precharge power entry down active power exit down active read (nop) t pdex ck ck nop nop a a a a a a a a t cke t cke dq dqs high-z note : 1) device must be in the all banks idle state prior to entering power down mode. 2) the minimum power down duration is specified by tcke. www.datasheet.co.kr datasheet pdf - http://www..net/
- 77 - - 77 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 20. clock stop stopping a clock during idle periods is an ef fective method of reducing power consumption. the lpddr sdram supports clock stop under the following conditions : - the last command (active, read, write, precharge, auto refres h or mode register set) has executed to completion, including an y data-out during read bursts; the number of clock pulses per ac cess command depends on the device?s ac timing parameters and the clock requency; - the related timing conditions(trcd, twr, trp, trfc, tmrd) has been met; - cke is held high when all conditions have been met, the device is either in "idle state"or "row ac tive state" and clock stop mode may be entered with ck held low and ck held hight. clock stop mode is exited by restarting the clock. at least one nop command has to be issued before the next access command any be applied. addi- tional clock pulses might be required de pending on the system characteristics. figure 17 shows clock st op mode entry and exit. - initially the device is in clock stop mode - the clock is restarted with the rising edge of t0 and a nop on the command inputs - with t1 a valid access command is latched; this command is followed by nop commands in order to allow for clock stop as soon as this access com- mand is completed. - tn is the last clock pulse requir ed by the access command latched with t1 - the clock can be stopped after tn. figure 17. clock stop mode entry and exit ck ck t0 t1 t2 tn cke timing condition command nop cmd nop nop nop address a a valid dq, dqs high-z clock stopped exit clock stop mode valid command enter clock stop mode = don?t care ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ www.datasheet.co.kr datasheet pdf - http://www..net/
- 78 - - 78 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary timing diagram www.datasheet.co.kr datasheet pdf - http://www..net/
- 79 - - 79 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 1. power up sequence for mobile ddr sdram figure 18. power up sequence for mobile ddr sdram cke cs ras cas addr ba0 ba1 dqs a10/ap ck ck dm precharge t rp | | | | key raa t rfc t rfc (all bank) auto refresh auto refresh normal mrs extended mrs row active (a-bank) | | | | | | | | | | | | | | : don?t care key high | | | | | | | | | | | | | | we | | | | key raa key hi-z hi-z hi-z | | | | note : 1) apply power and attempt to maintain cke at a high state and all other inputs may be undefined. - apply vdd before or at the same time as vddq. 2) maintain stable power, stable clock and nop input condition for a minimum of 200us. 3) issue precharge commands for all banks of the devices. 4) issue 2 or more auto-refresh commands. 5) issue a mode register set command to initialize the mode register. 6) issue a extended mode register set command for the desired operating modes after normal mrs. the mode register and extended mode register do not have default values. if they are not programmed during the initializati on sequence, it may lead to unspecified operation. all banks have to be in idle state prior to adjusting mrs and emrs set. www.datasheet.co.kr datasheet pdf - http://www..net/
- 80 - - 80 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 2. basic timing figure 19. basic timing (setup, hold and access time @bl=4, cl=3) 0123456789101112131415 cke cs ras cas a10/ap addr dqs (a0~an) dqs : don?t care ck ck high baa dm command active t rpre read write baa bab ra ra ca cb db0 db1 db2 db3 qa0 qa1 qa2 qa3 t ac t wpres t dqss t dsc t dqsh t dqsl t wpst t rpst t ds t dh t ck t ch t cl t ck t ch t cl t is t ih ba0, ba1 t wpreh we t dqsck hi-z hi-z hi-z hi-z hi-z hi-z t qhs www.datasheet.co.kr datasheet pdf - http://www..net/
- 81 - - 81 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 3. multi bank interleaving read figure 20. multi bank in terleaving read (@bl=4, cl=3) 0123456789101112131415 cke cs ras cas ba0,ba1 a10/ap addr dqs (a0~an) dqs : don?t care ck ck high baa dm command qa0 qa1 qa2 qa3 qb0 qb1 qb2 qb3 active t rrd t ccd bab baa bab ra ra rb ca cb active read read t rcd rb we hi-z hi-z www.datasheet.co.kr datasheet pdf - http://www..net/
- 82 - - 82 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 4. multi bank interleaving write figure 21. multi bank interleaving write (@bl=4) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cke cs ras cas ba0,ba1 a10/ap addr dqs (a0~an) dqs : don?t care ck ck high baa dm command da0 da1 da2 da3 db0 db1 db2 db3 active t rrd t ccd bab baa bab ra rb ca cb active write write t rcd we ra rb hi-z hi-z www.datasheet.co.kr datasheet pdf - http://www..net/
- 83 - - 83 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 5. read with auto precharge figure 22. read with auto precharge (@bl=8) 012345678910 cke cs ras cas a10/ap addr dqs dqs ba0,ba1 (a0~an) dm : don?t care ck ck high baa qa0 qa1 qa2 qa4 qa5 qa6 command read qa7 qa3 active ra ca ra (cl=3) (cl=3) auto precharge start t rp note 1) we baa hi-z hi-z note : 1) the row active command of the precharge bank can be issued after trp from this point. www.datasheet.co.kr datasheet pdf - http://www..net/
- 84 - - 84 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 6. write with auto precharge figure 23. write with auto precharge (@bl=8) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 auto precharge start cke cs ras cas ba0,ba1 a10/ap addr dqs (a0~an) dqs : don?t care ck ck high baa baa ra ca ra dm command da0 da1 da2 da3 da4 da5 da6 da7 write active note 1) t wr t rp we hi-z hi-z note : 1) the row active command of the precharge bank can be issued after trp from this point www.datasheet.co.kr datasheet pdf - http://www..net/
- 85 - - 85 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 7. write followed by precharge figure 24. write followed by precharge (@bl=4) 012345678910 cke cs ras cas a10/ap addr dqs dqs ba0,ba1 (a0~an) dm : don?t care ck ck high da0 da1 da2 da3 command write baa ca pre charge t wr baa we hi-z hi-z www.datasheet.co.kr datasheet pdf - http://www..net/
- 86 - - 86 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 8. write interrupted by precharge & dm figure 25. write interrupted by precharge & dm (@bl=8) 012345678910 cke cs ras cas a10/ap addr dqs dqs ba0,ba1 (a0~an) dm : don?t care ck ck high baa da0 da1 da2 da3 da4 da6 da7 command write da5 t wr bab bac baa ca cb cc db0 db1 dc0 dc2 dc3 dc1 t ccd pre charge write write we dc [ dc \ xx xy dc ] dc ^ x 3 hi-z hi-z www.datasheet.co.kr datasheet pdf - http://www..net/
- 87 - - 87 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 9. write interrupted by a read figure 26. write interrupted by a read (@bl=8, cl=3) 0123456789 cke cs ras cas a10/ap addr dqs dqs ba0,ba1 (a0~an) dm : don?t care ck ck high da0 da1 da2 da3 da4 da5 command write bab ca cb qb0 qb1 qb2 qb3 read t cdlr masked by dm baa we qb [ qb \ qb ] qb ^ 10 11 hi-z hi-z www.datasheet.co.kr datasheet pdf - http://www..net/
- 88 - - 88 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 10. read interrupted by precharge figure 27. read interrupted by precharge (@bl=8, cl=3) 012345678910 cke cs ras cas a10/ap addr dqs dqs ba0,ba1 (a0~an) dm : don?t care ck ck high qa0 qa1 qa2 qa3 qa4 command read baa qa5 pre baa ca charge 2 t ck valid we hi-z hi-z www.datasheet.co.kr datasheet pdf - http://www..net/
- 89 - - 89 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 11. read interrupted by a write & burst stop figure 28. read interrupted by a write & burst stop (@bl=8, cl=3) 012345678910 cke cs ras cas a10/ap addr dqs dqs ba0,ba1 (a0~an) dm : don?t care ck ck high qa0 qa1 qb0 qb1 qb2 qb4 qb5 qb6 command read baa qb7 qb3 burst bab ca cb write stop we 11 hi-z hi-z www.datasheet.co.kr datasheet pdf - http://www..net/
- 90 - - 90 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 12. read interrupted by a read figure 29. read interrupted by a read (@bl=8, cl=3) 012345678910 cke cs ras cas a10/ap addr dqs dqs ba0,ba1 (a0~an) dm : don?t care ck ck high baa qa0 qa1 qb0 qb1 qb2 qb4 qb5 qb6 command read bab ca cb qb7 qb3 read we hi-z hi-z www.datasheet.co.kr datasheet pdf - http://www..net/
- 91 - - 91 - K521F12ACD-B060 datasheet mcp memory rev. 0.0 preliminary 13. dm function figure 30. dm function (@bl=8) only for write 012345678910 cke cs ras cas a10/ap addr dqs dqs ba0,ba1 (a0~an) dm : don?t care ck ck high baa ca da0 da1 da2 da3 da5 da6 da7 command write da4 we hi-z hi-z www.datasheet.co.kr datasheet pdf - http://www..net/

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